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Electronics-and-communication-engineering0
Analog IC Design (View More...)
| Nyquist Criterion; Phase Margin | lec10 | 37:20 to 44:38 | VIDEO | |
| Phase Margin | lec11 | 10:30 to 16:50 | VIDEO | |
| Phase Margin | lec11 | 33:55 to 47:54 | VIDEO |
Communication Engineering (View More...)
| The Phase Locked Loop | lec23 | 01:08 to 04:45 | VIDEO | |
| The Phase Locked Loop | lec23 | 04:45 to 11:49 | VIDEO | |
| The Phase Locked Loop | lec23 | 11:49 to 16:03 | VIDEO |
Control Engineering M Gopal (View More...)
| Basic Principles of Feedback Control (Contdâ¦) | lec20 | 10:24 to 12:50 | VIDEO | |
| Basic Principles of Feedback Control (Contdâ¦) | lec20 | 33:11 to 35:50 | VIDEO | |
| The Nyquist Stability Criterion and Stability Margins | lec35 | 00:40 to 42:56 | VIDEO |
Electronics for Analog Signal Processing - II (View More...)
| PLL (PHASE LOCKED LOOP) | lec37 | 02:40 to 03:24 | VIDEO | |
| PLL (PHASE LOCKED LOOP) | lec37 | 03:24 to 04:23 | VIDEO | |
| PLL (PHASE LOCKED LOOP) | lec37 | 05:13 to 07:13 | VIDEO |
RF Integrated Circuits (View More...)
| Phase Locked Loop Basics | lec31 | 03:14 to 09:10 | VIDEO | |
| Phase Locked Loop Basics | lec31 | 12:46 to 17:56 | VIDEO | |
| Phase Locked Loop Basics | lec31 | 27:25 to 35:40 | VIDEO |
VLSI Circuits (View More...)
| Verilog Modeling of Combinational Circuits | lec10 | 40:43 to 52:48 | VIDEO | |
| Modeling of Verilog Sequential Circuits - Core Statements | lec11 | 04:32 to 07:15 | VIDEO | |
| Modeling of Verilog Sequential Circuits - Core Statements | lec11 | 10:45 to 14:35 | VIDEO |
VLSI Data Conversion Circuits (View More...)
| Excess Loop Delay (ELD) | lec32 | 00:37 to 06:21 | VIDEO | |
| Excess Loop Delay (ELD) | lec32 | 06:21 to 12:15 | VIDEO | |
| Excess Loop Delay (ELD) | lec32 | 12:15 to 15:21 | VIDEO |