Analog IC Design (View More...)
| Differential and Common Mode Half Circuits; Differential Pair with Active Load | lec29 | 20:30 to 25:43 | VIDEO | |
| Differential and Common Mode Half Circuits; Differential Pair with Active Load | lec29 | 25:43 to 28:39 | VIDEO | |
| Common Mode Rejection Ratio; Example | lec38 | 01:19 to 6:24 | VIDEO |
Communication Engineering (View More...)
| The Phase Locked Loop | lec23 | 01:08 to 04:45 | VIDEO | |
| The Phase Locked Loop | lec23 | 04:45 to 11:49 | VIDEO | |
| The Phase Locked Loop | lec23 | 11:49 to 16:03 | VIDEO |
Circuits for Analog System Design (View More...)
| AC- applications of the Op-Amp and Lock in Amplifier Design | lec33 | 29:12 to 31:04 | VIDEO | |
| Design of lock in Amplifier Circuit with example | lec34 | 04:21 to 06:15 | VIDEO | |
| Design of lock in Amplifier Circuit with example | lec34 | 13:03 to 16:16 | VIDEO |
Electronics for Analog Signal Processing - II (View More...)
| PLL (PHASE LOCKED LOOP) | lec37 | 07:13 to 11:08 | VIDEO | |
| PLL (Phase Locked Loop) (Continued) | lec38 | 28:22 to 29:35 | VIDEO | |
| Experimental Demonstration of Lock Range, Capture Range and FSK and FM Detection Using PLL | lec39 | 13:38 to 15:19 | VIDEO |