Coding Theory (View More...)
| Thresholds of LDPC Codes | lec25 | 00:24 to 06:17 | VIDEO | |
| Thresholds of LDPC Codes | lec25 | 39:52 to 45:17 | VIDEO |
Digital Circuits and Systems (View More...)
| Triggering Mechanisms of Flip Flops and Counters | lec19 | 30:20 to 39:40 | VIDEO | |
| Design of Synchronous Sequential Circuits | lec24 | 2:14 to 6:26 | VIDEO | |
| MSI and LSI based implementation of sequential circuits (contd...) | lec35 | 34:10 to upto | VIDEO |
Digital System Design (View More...)
| Combinational Logic Design using Programmable Arrays of Logic Gates | lec19 | 10:57 to 13:21 | VIDEO | |
| Combinational Logic Design using Programmable Arrays of Logic Gates | lec19 | 13:21 to 15:07 | VIDEO | |
| Combinational Logic Design using Programmable Arrays of Logic Gates | lec19 | 15:07 to 18:52 | VIDEO |
Engineering Physics II (View More...)
| Module No. # 03 | lec12 | 37:02 to 39:36 | VIDEO | |
| Module No. # 03 | lec16 | 36:14 to 39:08 | VIDEO | |
| Module No. # 03 | lec16 | 39:08 to 43:00 | VIDEO |
Probability and Statistics (View More...)
| Testing of Hypothesis-I | lec33 | 25:49 to 30:49 | VIDEO | |
| Testing of Hypothesis-I | lec33 | 30:49 to 36:27 | VIDEO | |
| Testing of Hypothesis-I | lec33 | 36:27 to 39:05 | VIDEO |
VLSI Circuits (View More...)
| Verilog Modeling of Combinational Circuits | lec10 | 11:25 to 13:26 | VIDEO | |
| Verilog Modeling of Combinational Circuits | lec10 | 35:26 to 37:21 | VIDEO | |
| Design Flow of VLSI Circuits | lec23 | 17:00 to 25:29 | VIDEO |