Gate Material Placement Ready Login Sign up Login Sign up

GATE ECE - Important Keywords

Boolean postulates
Boolean laws
DeMorgans Theorem
Principle of Duality
Duality principles
Boolean expression
Boolean expressions
Boolean expression minimization
Minterm
Maxterm
Sum of Products
SOP
Product of Sums
POS
Karnaugh map
Karnaugh map Minimization
map Minimization
Dont care conditions
Quine Mc Cluskey method
Logic Gates
Gates
AND
OR
NOT
NAND
NOR
Exclusive OR
Exclusive NOR
Logic Functions using gates
NAND
NOR implementations
gate implementations
Gate level
output Gate
Multi level gate implementations
Multi output gate implementations
Transistor Transistor Logic
TTL
CMOS Logic
complementary metal oxide semiconductor
CMOS Logic characteristics
Tristate gates
adder
Half adder
Full Adder
subtractor
Half subtractor
Full subtractor
binary adder
Parallel binary adder
binary Subtractor
parallel binary Subtractor
Fast Adder
Ahead adder
Carry Look Ahead adder
Serial Adder
Serial Subtractor
Binary Coded Decimal adder
BCD adder
Binary Multiplier
Binary Divider
Multiplexer
Demultiplexer
decoder
encoder
parity checker
checkers
parity generators
code converters
Magnitude Comparator
Comparator
Latches
Flip flops
SR Flip flops
JK Flip flops
D Flip flops
T Flip flops
Master Slave
Characteristic table
Characteristic equation
Application table
table applications
Edge triggering
triggering
Level Triggering
flip flops Realization
serial adder
serial subtractor
Asynchronous Ripple
Ripple
serial counter
Asynchronous Up counter
Asynchronous Up counter
Down counter Synchronous counters
Programmable counters
Synchronous counters Design
state diagram
State table
State minimization
State assignment
Excitation table
maps Circuit implementation
Modulo n counter
n counter
Registers
shift registers
Universal shift registers
Shift register counters
Ring counter
counter
Shift counters
Sequence generators
Classification of memories
Memories classification
Read only Memory
ROM
Read only Memory organization
ROM organization
read only memory
programmable read only memory
PROM
Erasable programmable read only memory
EPROM
Electrically erasable programmable read only memory
EEPROM
Electronically Alterable Programmable Read Only Memory
EAPROM
Random access memory
RAM
RAM organization
Write operation
Read operation
Memory cycle
Timing wave forms
Memory decoding
memory expansion
RAM Cell
Static RAM Cell
Bipolar RAM cell
MOSFET RAM cell
Dynamic RAM cell
Programmable Logic Devices
PLD
Programmable Logic Array
PLA
Programmable Array Logic
PAL
Field Programmable Gate Arrays
FPGA
combinational logic circuits using ROM
logic circuits using ROM
Synchronous Sequential Circuits
Sequential Circuits
General Model
Algorithmic State Machine
State Machine
Synchronous Sequential Circuits
Asynchronous Sequential Circuits
fundamental mode circuits
pulse mode circuits
State Machines
Asynchronous Circuits Problems
Free Switching circuits
Hazard Free Switching circuits Design
Switching circuits design
Combinationalcircuits
Sequential circuits
Combinationalcircuits using VERILOG
Sequential circuits using VERILOG
VERILOG
Any Queries, please contact us @ 09677117110 or mail to NPTEL.Bodhbridge@btechguru.com
Distributed under Creative Commons Attribution-Share Alike - CC BY-SA.
Back to top
View Cart & Pay (0)