+91-9003106272
(9.30 am to 7.30 pm)
Contact Us
About Us
Students
Colleges
Franchisee
Gate Material
Placement Ready Login
Login
Sign up
Login
Sign up
Forgot Password
Forgot User Name
Forgot Password
Forgot User Name
Sign up
Home
Placement Ready
My Choice My Future
Courses
Beat Score
Open Courseware
Study Abroad
Funda Spring
Students
Colleges
Franchisee
GATE ECE
GATE CSE
Anna University - ECE
Anna University - CSE
Search
GATE ECE - Important Keywords
CPU fundamentals
Control Processing unit
Memory
IO
Input output
Technology trends
power energy
Power cost
Dependability
Computer Performance
Computer Evaluation
Instruction level parallelism
ILP concepts
parallelism
Pipelining
Compiler Techniques
Exposing ILP
Dynamic Branch Prediction
Prediction
Branch Prediction
Dynamic Scheduling
Scheduling
Multiple instruction Issue
instruction Issue
Hardware Speculation
Static scheduling
Multithreading
ILP Limitations
Vector architecture
SIMD extensions
Single Instruction Multiple Data
Graphics Processing units
Graphics unit
Loop level parallelism
parallelism
Symmetric Shared Memory Architectures
Shared Memory Architectures
Memory Architectures
Distributed Shared Memory Architectures
Synchronization
Memory models
Memory Consistency
Intel i7 Processor
i7 Processor
processor
Simultaneous multithreading
SMT Processors
multithreading
chip multiprocessor
CMP Processors
Cache Performance
Cache Miss Penalty
Cache Miss Rate
Cache Reducing
Reducing Hit Time
Hit Time
Main Memory Performance
Main Memory
Memory Technology
Storage Devices
Storage types
Buses
RAID
Reliability
Memory Availability
Memory Dependability
Input output performances
I/O Performance Measures
Gate ECE
Gate CSE
Anna University - CSE
Anna University - ECE
Any Queries, please contact us @ 09677117110 or mail to NPTEL.Bodhbridge@btechguru.com
Distributed under Creative Commons Attribution-Share Alike - CC BY-SA.
Back to top
View Cart & Pay
(
0
)