| Abstract: |
Design: Hierarchy, controller (FSM), case study, meta-stability, synchronization, FSM issues, timing issues, pipelining, resource sharing.
VHDL: Different models, simulation cycles, process, concurrent and sequential statements, loops, delay models, library packages, functions, procedures, synthesis, test bench.
PLD: SPLD and CPLD architecture, timing, applications.
FPGA: Logic block and routing architecture, Virtex-II, Stratix architectures, constraints, STA, case study.
Hardware-software co-simulation, bus function models, SoPC. |
Electronics & Communication Engineering
Digital System design with PLDs and FPGAs
