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# Lecture Name
Title: Advanced Logic Synthesis
Department: Electronics & Communication Engineering
Author: Dhiraj Taneja
University: Broadcom, Hyderabad
Type: WebLink

1. The goal of the course is to study the components of digital design & advanced concepts in synthesis process
2. To understand the importance of technology, libraries, design constraints, design rules
3. To understand the usefulness of reports with respect to design on Area, Timing & Power

Learning Outcomes:

1. Ability to set constraints, Validate the results and analyze the reports
2. Ability to synthesize the design based on Area and Timing priority
3. Ability to perform critical path synthesis
4. Ability to perform timing analysis on the synthesized netlist
5. Ability to verify the functional equivalence of the synthesized netlist Vs RTL
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