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Computer Science and Engineering  Design Verification and Test of Digital VLSI Circuits
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# Lecture Name
Title: Design Verification and Test of Digital VLSI Circuits
Department: Computer Science and Engineering
Author: Prof. Jatindra Kumar Deka, Dr. Santosh Biswas
University: IIT Guwahati
Type: WebLink
Abstract: Digital VLSI Design flow comprises three basic phases: Design, Verification and Test. The video course would cover theoretical, implementation and CAD tools pertaining to these three phases. Although there can be individual full courses for each of these phases, the present course aims at covering the important problems/algorithms/tools so that students get a comprehensive idea of the whole digital VLSI design flow.
VLSI Design: High level Synthesis, Verilog RTL Design, Combinational and Sequential Synthesis Logic Synthesis (for large circuits).
Verification Techniques: Introduction to Hardware Verification and methodologies, Binary Decision Diagrams(BDDs) and algorithms over BDDs, Combinational equivalence checking, Temporal Logics, Modeling sequential systems and model checking, Symbolic model checking.
VLSI Testing: Introduction, Fault models, Fault Simulation, Test generation for combinational circuits, Test generation algorithms for sequential circuits and Built in Self test.
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