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Computer Science and Engineering  Low Power VLSI Circuits & Systems
   
 
Title: Low Power VLSI Circuits & Systems
Department: Computer Science and Engineering
Author: Prof. Ajit Pal
University: IIT Kharagpur
Type: WebLink
Abstract: Power consumption is the bottleneck of system performance and is listed as one of the top three challenges in ITRS 2008. Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper first gives a brief overview for low power optimization techniques at system and architecture level, then focus discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems.
 
   
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